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High-Speed LVDS (SERDES) Transceiver
High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS links such as Channel-link®, Camera-link®, FPD-link®, FlatLink®, MIPI etc.
Capable of data rates of up to 500 MBits/s per lane on basic FPGA devices and 1 Gbits/s+ on higher-end FPGAs.
Capable of data rates of up to 500 MBits/s per lane on basic FPGA devices and 1 Gbits/s+ on higher-end FPGAs.
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Block Diagram of the High-Speed LVDS (SERDES) Transceiver IP Core
