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High-Speed LVDS (SERDES) Transceiver
High-speed LVDS (SERDES) transceiver with up to 8 serial data lanes, generic data width and integrated asynchronous FIFO. Ideal for standard LVDS links such as Channel-link®, Camera-link®, FPD-link®, FlatLink®, MIPI etc.
Capable of data rates of up to 500 MBits/s per lane on basic FPGA devices and 1 Gbits/s+ on higher-end FPGAs.
Capable of data rates of up to 500 MBits/s per lane on basic FPGA devices and 1 Gbits/s+ on higher-end FPGAs.
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Block Diagram of the High-Speed LVDS (SERDES) Transceiver IP Core
LVDS IP
- Bi-Directional LVDS with LVCMOS
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane