English
You are here:
HSSTP TX PHY 5nm Samsung Foundry
The sf_hsstp13b2t_ln05lpe is a hard macro IP implementing the ARM HSSTP PHY Layer for Samsung's 5nm process technology. This IP enables SoCs to serially transmit high bandwidth data off-chip, achieving speeds up to 6Gbps per lane.
It offers variable data rates with a fractional-N (Frac-N) RO PLL and configuration options for 1 or 2 lanes, I/O pads and ESD protection are included along with at-speed BIST and scan test functionalities for stramlined integration and reliable performance.
It offers variable data rates with a fractional-N (Frac-N) RO PLL and configuration options for 1 or 2 lanes, I/O pads and ESD protection are included along with at-speed BIST and scan test functionalities for stramlined integration and reliable performance.
View HSSTP TX PHY 5nm Samsung Foundry full description to...
- see the entire HSSTP TX PHY 5nm Samsung Foundry datasheet
- get in contact with HSSTP TX PHY 5nm Samsung Foundry Supplier
Block Diagram of the HSSTP TX PHY 5nm Samsung Foundry
