I2C Master / Slave Controller w/FIFO (APB Bus)

The I2C Master / Slave Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master / slave controller and one or more master, slave, or master / slave devices on the I2C Bus.

• see the entire I2C Master / Slave Controller w/FIFO (APB Bus) datasheet
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