I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)

The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master / slave controller and one or more master / slave devices. The companion products, the DB-I2C-MS-APB, DB-I2C-MS-AHB, DB-I2C-MS-AVLN, DB-I2C-MS-AXI-Lite, support on-chip bus interfaces with microprocessors such as the ARM, MIPS, PowerPC, and ARC.

Digital Blocks offers I2C Controller Master/Slave, Master only, and Slave only IP with AXI / AHB / APB / Avalon / Qsys Interfaces. In addition, besides interfacing to a CPU, the I2C Controllers can transfer blocks of data directly between System Memory or Registers and the I2C Bus.

• see the entire I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) datasheet
• get in contact with I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus) Supplier