I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)

The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or other high performance microprocessor via the AMBA APB or AHB or AXI-Lite or Altera Avalon System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more master / slave or slave devices.

Digital Blocks offers a I2C Controller Slave only function with FIFOF and interface to APB / AHB / AXI-lite / Avalon Interconnect. This enables a Microprocessor via the FIFO and DB-I2C control to interfaces as a I2C Slave device to ttransfers data with an external I2C master.

In addition, besides interfacing to a CPU, the I2C Slave Controllers can DMA transfer blocks of data directly between System Memory or Registers and the I2C Bus.

• see the entire I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus) datasheet
• get in contact with I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus) Supplier