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Image Signal Procesing, Real-time Pixel Processor Automotive
Dream Chips Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed for high-performance imaging applications. The processing pipeline consists of all necessary modules allowing to output HDR tone-mapped images of highest possible quality.
In addition, the RPP provides measurement values in real-time to implement auto-exposure, auto-white balance, and auto-focus functionality, addressed as 3A functionality.
The hardwired nature of the RPP guarantees lowest latency and power consumption with only 5 MIPS software processing need per frame.
It accepts YCbCr or RGB Bayer input data in ITU-R BT.601 or ITU-R BT.656 sync mode and can be connected via MIPI serial interfaces. The RPP provides configurable input and output data widths. It supports input image frames with 8, 10, 12, 14, 16, 20 and 24-bit amplitude resolutions, while it can output meticulously tone-mapped frames with 10- or 12-bit per pixel.
Furthermore, the RPP provides a 16-bit DMA data interface as an alternative input path, and a 32-bit PVCI configuration interface. The input part of the ISP is fully programmable in terms of signal polarities, active video data positions, and luminance-chrominance or bayer pattern order.
The RPP ISP has two parallel outputs, one for human vision and one for machine vision.
The IP supports ASIL D (systematic) and ASIL B (hardware integrity) in accordance with ISO 26262:2018.
In addition, the RPP provides measurement values in real-time to implement auto-exposure, auto-white balance, and auto-focus functionality, addressed as 3A functionality.
The hardwired nature of the RPP guarantees lowest latency and power consumption with only 5 MIPS software processing need per frame.
It accepts YCbCr or RGB Bayer input data in ITU-R BT.601 or ITU-R BT.656 sync mode and can be connected via MIPI serial interfaces. The RPP provides configurable input and output data widths. It supports input image frames with 8, 10, 12, 14, 16, 20 and 24-bit amplitude resolutions, while it can output meticulously tone-mapped frames with 10- or 12-bit per pixel.
Furthermore, the RPP provides a 16-bit DMA data interface as an alternative input path, and a 32-bit PVCI configuration interface. The input part of the ISP is fully programmable in terms of signal polarities, active video data positions, and luminance-chrominance or bayer pattern order.
The RPP ISP has two parallel outputs, one for human vision and one for machine vision.
The IP supports ASIL D (systematic) and ASIL B (hardware integrity) in accordance with ISO 26262:2018.
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