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InfiniBand Transport Layer Cores
Polybus offers a family of InfiniBand Transport Layer Cores for use in Data Acquisition, High Performance Computing and Networking Applications.
For Data Acquisition and Networking applications, Polybus offers a 4X Single Data Rate (SDR) Unreliable Connect (UC) Transport Layer Core which supports UC SEND and UC RDMA Write on 1024 simultaneous Queue Pairs. The Core operates at full wire speed when mated with the Polybus SDR Link Layer core. Message sizes of up to 2GBytes are supported.
For High Performance Computing applications, Polybus offers a 4X SDR Reliable Connect (RC) Transport Layer Core. The core handles both reliable and unreliable connections, supports RDMA Read, RDMA Write and SEND operations. The RC Transport Layer also has support for End to End Flow control. The design is optimized for low latency and maximum throughput even on small packet sizes. The buffers can operate in cut-through mode to minimize latency. The core supports 1024 Queue Pairs and 511 Reliable Requests in flight at any one time. Retries are handled completely independently from the client logic. The Advanced Transport Layer Core implements the InfiniBand Architecture Release 1.2 Transport Layer specification.
Both the UC Transport Layer Core and the RC Transport Layer Core are available for the Xilinx Virtex2P, Virtex4FX and Virtex5 FPGAs, other FPGA families are available on request.
A DDR Transport Layer Core is planned for 2007.
For Data Acquisition and Networking applications, Polybus offers a 4X Single Data Rate (SDR) Unreliable Connect (UC) Transport Layer Core which supports UC SEND and UC RDMA Write on 1024 simultaneous Queue Pairs. The Core operates at full wire speed when mated with the Polybus SDR Link Layer core. Message sizes of up to 2GBytes are supported.
For High Performance Computing applications, Polybus offers a 4X SDR Reliable Connect (RC) Transport Layer Core. The core handles both reliable and unreliable connections, supports RDMA Read, RDMA Write and SEND operations. The RC Transport Layer also has support for End to End Flow control. The design is optimized for low latency and maximum throughput even on small packet sizes. The buffers can operate in cut-through mode to minimize latency. The core supports 1024 Queue Pairs and 511 Reliable Requests in flight at any one time. Retries are handled completely independently from the client logic. The Advanced Transport Layer Core implements the InfiniBand Architecture Release 1.2 Transport Layer specification.
Both the UC Transport Layer Core and the RC Transport Layer Core are available for the Xilinx Virtex2P, Virtex4FX and Virtex5 FPGAs, other FPGA families are available on request.
A DDR Transport Layer Core is planned for 2007.
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