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INNOLINK-C PHY
Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to-Die and Chip-to-Chip IP family:
Innolink-A, SerDes-based, up to 32 or 56Gbps/pair, long-reach, chip to chip or board to board connection.
Innolink-B, GDDR-like, single-ended, up to 24Gbps/pin, typical MCM or short PCB application, with bump pitch of 100um~150um. Innolink-B is compatible with UCIe standard package version at physical layer, and Innosilicon is developing UCIe adapter layer and protocol layer. If customer don’t need the compatibility with third-party chiplet connection, Innosilicon can provide silicon proven Innolink controller solution. Please find detailed information at Innolink Controller databook.
Innolink-C, GDDR-like and LPDDR5-like, optimized for silicon interposer, super small IO and 0.4V IO voltage, up to 24Gbps/pin, with bump pitch of 40um~100um. Innolink-C is compatible with UCIe advanced package version at physical layer, and Innosilicon is developing UCIe adapter layer and protocol layer. If customer don’t need the compatibility with third-party chiplet connection, Innosilicon can provide silicon proven Innolink controller solution. Please find detail information at Innolink Controller databook.
Innosilicon can provide the PHY solution, as well as PHY + Controller solution. The PHY is provided as a full harden IP, while Controller is provided as a soft IP. This databook is for Innolink-C PHY solution with DFI-like interface.
INNOLINK-C is designed to perform high speed data communication between dies. The physical implementation methodology of INNOLINK-C is a DDR-like interface, which use single ended signal for IO interface, forward clock is used for Rx data sampling.
For this process, The Innolink-C speed up to 12Gbps per DQ.
By default, Innolink-C adopts 64-bit Tx DQs and 64-bit Rx DQs per module, when each DQ runs at 12Gbps with two modules equipped (64-bit Tx + 64-bit Rx) * 2, it provides a total bandwidth of 1.536Tbps for Tx and 1.536Tbps for Rx. Innolink-C can be configured to 1/2/4/8/16/32 modules, and this datasheet is an example of 1 module configuration (64-bit Tx + 64-bit Rx).
Innolink can be easily integrated with Innolink controller, and IO input/output direction can be software defined.
Innolink-A, SerDes-based, up to 32 or 56Gbps/pair, long-reach, chip to chip or board to board connection.
Innolink-B, GDDR-like, single-ended, up to 24Gbps/pin, typical MCM or short PCB application, with bump pitch of 100um~150um. Innolink-B is compatible with UCIe standard package version at physical layer, and Innosilicon is developing UCIe adapter layer and protocol layer. If customer don’t need the compatibility with third-party chiplet connection, Innosilicon can provide silicon proven Innolink controller solution. Please find detailed information at Innolink Controller databook.
Innolink-C, GDDR-like and LPDDR5-like, optimized for silicon interposer, super small IO and 0.4V IO voltage, up to 24Gbps/pin, with bump pitch of 40um~100um. Innolink-C is compatible with UCIe advanced package version at physical layer, and Innosilicon is developing UCIe adapter layer and protocol layer. If customer don’t need the compatibility with third-party chiplet connection, Innosilicon can provide silicon proven Innolink controller solution. Please find detail information at Innolink Controller databook.
Innosilicon can provide the PHY solution, as well as PHY + Controller solution. The PHY is provided as a full harden IP, while Controller is provided as a soft IP. This databook is for Innolink-C PHY solution with DFI-like interface.
INNOLINK-C is designed to perform high speed data communication between dies. The physical implementation methodology of INNOLINK-C is a DDR-like interface, which use single ended signal for IO interface, forward clock is used for Rx data sampling.
For this process, The Innolink-C speed up to 12Gbps per DQ.
By default, Innolink-C adopts 64-bit Tx DQs and 64-bit Rx DQs per module, when each DQ runs at 12Gbps with two modules equipped (64-bit Tx + 64-bit Rx) * 2, it provides a total bandwidth of 1.536Tbps for Tx and 1.536Tbps for Rx. Innolink-C can be configured to 1/2/4/8/16/32 modules, and this datasheet is an example of 1 module configuration (64-bit Tx + 64-bit Rx).
Innolink can be easily integrated with Innolink controller, and IO input/output direction can be software defined.
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