Interleaver/De-Interleaver
The Lattice Interleaver/de-interleaver IP core supports rectangular block type and convolutional architectures. Rectangular interleaving arranges the input data row-wise in a matrix. The interleaved data is obtained by reading the columns of the matrix. Convolutional interleaving feeds the input data to a number of branches, each of which has a shift register with pre-defined length. The output data is taken from the branch outputs. Lattice’s Convolutional Interleaver/de-interleaver IP Cores are compliant with ATSC and DVB standards, while the Rectangular Interleaver/de-interleaver is compliant with IEEE 802.16a standard.
View Interleaver/De-Interleaver full description to...
- see the entire Interleaver/De-Interleaver datasheet
- get in contact with Interleaver/De-Interleaver Supplier
Block Diagram of the Interleaver/De-Interleaver IP Core
FPGA IP
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Complete USB Type-C Power Delivery PHY, RTL, and Software
- Ethernet TSN Switch IP Core - Efficient and Massively Customizable
- CXL 2.0 Agilex FPGA Acclerator Card
- PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes