Internallly Compensated LDO - 100mA Output
(LDO), linear regulator for integration in a SoC.
The LDO uses advanced control techniques to
achieve excellent transient response, excellent
PSRR performance and low noise.
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Analog & Mixed Signal IP
- The tADC106-SW1-LR.01 is a mixed (analog and digital) Virtual Component (ViC) containing a three-channel ADC and additional functions offering an ideal mixed signal front end for low power and high quality audio applications.
- 7-bit, 64 GSPS ADC Ultra Low Power
- USB2.0 Host Transceiver PHY
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Fibre-Channel Transceiver
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro