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Universal Chiplet Interconnect Express (UCIe) Controller

• Up to 32 GT/s Per Lane.
• Up to 512 Gbps Aggregate Bandwidth.
• Support PCIe 7.0/6.0 CXL Streaming mode.

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v3.5 & C-PHY v2.1
• Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
• Consists of 3 Data lanes in C-PHY mode

5.8GHz Fractional-N PLL synthesizer

• Power supply 1.3V…1.98V
• Fractional PLL
• Two-point frequency modulation (BFSK) support

PCIe 5.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)

• Fully integrated multi-protocol turnkey platform in TSMC 12nm FFC+ for integration into Smart Edge AIoT SoCs

UCIe-S PHY, Standard Package

• Compliant to UCIe 2.0 specifications
• Supports MCM, BGA and Chiplet2Chiplet interconnects on PCB
• Speed up to 32GT/s per lane (insertion loss and process dependent)

PCIe 6.2 Switch IP Controller

• Compliant with PCIE Gen6/5/4/3/2/1 spec
• Data rate supports Gen 1/2/3/4/5/6
• Pipe 64bits

ONFI 4.0 NAND Flash PHY upto 800Mbps

• ONFI 1/2/3/4/5 compliant;
• Toggle/Toggle2 mode;
• Maximum 2400Mbps; (PHY_CLK = 1200Mhz)

8kx8 Bits OTP (One-Time Programmable) IP, X-FA- 0.18μm XH018 Modular Mixed Signal Process

• Fully compatible with X-FA- 0.18μm XH018 process
• Wide operating voltage range: 1.8 V ± 10% read voltage and 3.75 V ± 5% program voltage

RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing

• RTP/UDP/IP Protocol Hardware Stack,
• targets H.264 NAL Streams

Flash Memory LDPC Decoder

• Quasi cyclic (QC) – Algebraic constructed – LDPC Code
• Regular Parity Check Matrix
• Codeword length: 16 K

5-60V Input Buck Regulator (Type-C EPR compatible)

• Wide operating voltage range 4.5V – 60V.
• Output voltage optionally 5V, or 3.3V.
• Soft start.

DDR4 Memory Controller

1.6T Ultra Ethernet IP Solution with PHY, Controller and Verification IP

• Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
• Supports evolving IEEE 802.3 and OIF-224G electrical standards

1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes

• High speed performance
• Low power architecture
• Sub-sampling clock multiplier

28G Ethernet PHY IP for TSMC N7

• Supports 1.25 to 32 Gbps data-rate
• Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, CXL, and SATA protocols

UCIe PHY & D2D Adapter

• 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
• UCIe v1.1 specification

Multi-protocol SerDes PMA

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

NPU IP for Embedded AI

• Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code

Passive/active NFC transceiver

• TSMC 180 nm 6 metals generic process without analog options
• Differential antenna interfaces with dedicated external capacitors for antenna impedance matching

2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

• Efficiency
• Composability
• Programmability

I3C Host Controller

• Compliant with MIPI I3C Specification V1.0
• Supports up to 12.5 MHz operation using Push-Pull.

112G Ethernet PHY in TSMC (N7, N5, N3P)