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1.6T Ultra Ethernet IP Solution with PHY, Controller and Verification IP

• Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
• Supports evolving IEEE 802.3 and OIF-224G electrical standards

MIPI SPMI Host Controller

• Compliance as per MIPI Alliance Specifiction version 2.0
• Support SCLK frequency Low Speed - 32kHz to 15MHz
• Support SCLK frequency High Speed - 32kHz to 26MHz

24-bit 1-channel 44.1 to 48kSPS delta-sigma ADC

• XFAB XT018 SOI 180nm
• Resolution 24 bit
• Sampling rate 44.1kSPS to 48kSPS

DRBG IP Core

• Perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'.

Single port SRAM Compiler - low power retention mode

• Ultra-Low Leakage
• Bit Cell
• Ultra Low Power Standby

MIPI D-PHY Universal IP in UMC 28HPC+

• Supports MIPI Alliance Specification for D-PHY Version 2.5
• Consists of 1 Clock lane and 4 Data lanes
• Embedded, high performance, and highly programmable PLL

Low Dropout (LDO) Capless Regulator

• Input voltage of 1.2V
• Output voltage of 0.84V to 0.93V
• Up to 300mA output current

HBM3 PHY on TSMC N3P

• Low latency, small area, low power
• Compatible with JEDEC standard HBM3 DRAMs
• Data rates up to 9600 Mbps

Camera Demosaicing IP - DAISY (RCCC)

• Maximum Resolution: 8MP (3840h x 2160v)
• Maximum Input Frame Rate: 30fps
• Low Power Consumption

Scalable, On-Die Voltage Regulation for High Current Applications

• Enables per-core DVFS
• Localized IR drop mitigation
• Unlocks virtual power islands

Ultra Compact Ethernet TSN End Station Controller IP for Automotive

• Fully integrated hardware and software solution
• One physical Ethernet port and dedicated host port

0.6V/10uA, 20uA Bandgap and V2I converter (Voltage to current)

• TSMC MSRF CMOS 55nm
• Dual output reference voltage without trimming 0.6V±3.4%
• Buffered output

12-bit SAR ADC TSMC

SafeSPI Controller

• Compliant to SafeSPI Rev 2.0.
• Master, slave, or monitor roles
• All frame formats

MIPI DPHY in GF 22FDSOI18 for Automotive

• Compliant with the MIPI D-PHY specification
• Fully verified hard macro
• Up to 2.5 Gb/s per lane

PCIe 6.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 6.0, encoding, backchannel initialization
• Supports PCIe Lane Margining at Receiver

Scalable, On-Die Voltage Regulation for High Current Applications

• Enables per-core DVFS
• Localized IR drop mitigation
• Unlocks virtual power islands

AES GCM IP Core

• supports encryption and decryption for modes listed below:
• supports offline and online key schedule
• supports 128, 192 and 256-bit key lengths
• has masked and non-masked modes

Multi-protocol SerDes PMA

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

Intra-Panel Multi Strandard TX 8nm

• COG and COF transmitter
• Data Rate : 120M ~ 4.0Gbps
• Supports Power Down and Low-Power modes during V-blank period

40G UCIe PHY IP on Samsung SF4X

• Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
• Compliant with the latest UCIe specification

eMMC LDPC Encoder/Decoder

• Supports data rates from 50 MB/s to 9.0 GB/s.
• Enables custom LDPC core development for specific requirements.
• Wide range of codeword sizes.

12-Bit 125MS/s Pipelined ADC