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30mA, Capless High PSRR LDO Regulator for RF and Analog Applications in TSMC 28nm

• No input or output capacitor required
• Input voltage from 1.65V to 2.0V
• Programmable output voltage of 0.9V, 1V, 1.2V, 1.3V

Agile ECC/RSA Public Key Accelerator with 128-bit ALU

• Offloads computationally intensive parts of public key cryptography
• Support for Arm® AMBA® AHB™/AXI™ and synchronous RAM slave interfaces

PCIe - PCI Express Controller

• Fully synthesizable Register Transfer Level (RTL) Verilog HDL core
• Test Bench. (Environment Variable : Verilog)
• Methodologies - based Test Bench : UVM

PCIe 4.0 PHY on 5nm

• Low power consumption and small area
• Support 1-, 2- and 4- lane configurations
• Automatic built-in self-test (Loopback)

30MHz Differential Line Receiver - X-FAB 0.35um

• High Voltage : 14V
• Wide Input Swing : 4Vp-p
• With Termination

PCIe 6.2 Switch

• 1 upstream port, up to 7 downstream ports
• Up to 128 lanes
• Up to x16 link width per port

32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM

• 2 different packages with or without vector: A46MPV, A46MP
• in-order dual-issue 8-stage CPU core with up to 256-bit VLEN
• Symmetric multiprocessing up to 16 cores

MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP

• Compliant with MIPI D-PHY v2.5 and C-PHY v2.0 specifications
• Supports MIPI DSI and CSI-2 protocols
• Supports HS data rates up to 6.5Gbps (6.5Gsps) per lane (per trio)

ARC Functional Safety Processor Software

• ASIL-D certified software that implements external software-based hardware safety mechanism provided for EM22FS, HS4xFS, EV7xFS, VPX5FS processors

3.3V to 1.8V Linear Voltage Regulator

• 14nm Low Power Plus (LN14LPP) CMOS device technology
• 3.3V±10%, 0.8V±5% dual power supply
• Operational Junction Temperature(Tj): -40℃~125℃

EXFAT IP Soft Core for NVMe

• Able to manage several disk in RAID0
• Same speed as in raw data format
• Support only 512-Byte LBA unit

24-bit 19.2Ksps Analog front end (AFE) having sigma delta ADC for Industrial process control and low power sensors

• Ultra-low power delta sigma ADC
• High performance up-to 124dB dynamic range
• Industry best IP specifications

UCIe Die-to-Die Chiplet Controller

• AXI over UCIe Streaming Protocol
• Link Error Detection and Retry Feature
• APB for Controller Control

UFSHCI 4.0

• Compliant with JEDEC UFSHCI Standard version 4.0 specification
• Compliant with JEDEC UFS Standard version 4.0 specification

JESD204D Transmitter and Receiver IP

• Designed according to JEDEC JESD204D Standard.
• Supports up to 24 lanes per IP cores.

Fractional-N Frequency Synthesizer PLL

• Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
• Input & output frequency ranges greater than 1000:1

HBM4 Memory Controller

• Supports HBM4 memory devices
• Supports all standard HBM4 channel densities (up to 32 Gb)
• Supports up to 10 Gbps/pin

Bi-Directional LVDS with LVCMOS

Multi-protocol SerDes PMA

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

Sub-GHz 330 to 470 MHz Ultra Low Power Transceiver IP

• Multi-Band
• Supply Voltages Core: 1.2V +/-10%, I/O: 2.0-3.6V
• Junction Temperature Range -40 to +85C

Low-Latency SerDes PMA

• Very wide CDR range - operates with data rates from 0.6Gbps to 4.0Gbps
• Compatible with JESD204A, JESD204B, OIF-CEI-6G-SR, CPRI, SGMII, XAUI and V-by-One

Integer-N Frequency Synthesizer PLL

7.5 Gbps DDR CML IPs library

• TSMC 40nm LP process
• 2.5V IO voltage supply
• 1.1V core voltage supply

12-bit SAR ADC TSMC