IPsec
Xiphera's scalable extreme-speed IPsec IP core is tailored for high-bandwidth applications, ranging from 10 Gbps to 200 Gbps links. Designed for seamless integration, our IP core supports a vendor-agnostic design methodology, making it adaptable across various high-end FPGA or ASIC environments.
Rapid ESP packet encryption/decryption
Packet processing performed in five different modes: authentication and encryption with or without Initialisation Vector, or passing payload as it is.
IPsec implementation can be adapted with enhancements and optimisations, based on customer requirements and the selected hardware architecture.
View IPsec full description to...
- see the entire IPsec datasheet
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Block Diagram of the IPsec IP Core
Video Demo of the IPsec IP Core
How to secure device communications and the rapidly growing Internet of Things?
This webinar presents implementations of MACsec, IPsec, and TLS on hardware devices, and explores the similarities and differences between the three security protocols. We will hear insights and guidance in the implementation decisions facing designers and architects responsible for ensuring secure connectivity.