IPSEC (RFC 4303) 1Gbit IP Core
The IPSec core includes a VHDL testbench which generates a sequence of test packets and compares the responses of the IP core to the output generated by a behavioral model of IPSec. It is supplied as VHDL source code and can be configured using a number of VHDL generic parameters to select only those features which are required in order to conserve area. The IPSec core provides both transmit and receive channels. The core is an easy to use fully synchronous design with a single clock and separate flow control on the transmit and receive channels. The core has been designed for efficiency in modern FPGAs and makes full use of FPGA specific features such as dual port memory blocks.
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