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ISDB-T Demodulator IP Core
The ISDB-T Demodulator IP Core is a 3-layer ISDB-T hierarchical demodulator compatible with the ARIB STD-B31 standard for Terrestrial Integrated Services Digital Broadcasting.
The ISDB-T Demodulator IP Core connects to an RF frontend via one or two ADCs (real or complex baseband) and performs the necessary processing to recover 3 separate transport streams carried on 3 separate layers within an ISDB-T broadcast channel. Sophisticated error-correction and channel equalisation techniques ensure excellent performance whilst ready access to error-rate metrics allows real-time system operation to be monitored and optimised.
The ISDB-T Demodulator provides fully automatic detection of received signal parameters and can be configured to search across any combination of ISDB-T transmission modes, guard intervals, and bandwidth settings. Modulation parameters are extracted from the embedded Transmission and Multiplexing Configuration Control (TMCC) channel and used to dynamically configure the demodulator without the need for any intervention from the host microprocessor.
A test data capture facility at points along the signal chain and a flexible microprocessor interface aids easy integration with your system. The design is available now as an efficient implementation for Xilinx FPGAs. Other FPGA’s and ASICs can also be supported on request.
The ISDB-T Demodulator IP Core connects to an RF frontend via one or two ADCs (real or complex baseband) and performs the necessary processing to recover 3 separate transport streams carried on 3 separate layers within an ISDB-T broadcast channel. Sophisticated error-correction and channel equalisation techniques ensure excellent performance whilst ready access to error-rate metrics allows real-time system operation to be monitored and optimised.
The ISDB-T Demodulator provides fully automatic detection of received signal parameters and can be configured to search across any combination of ISDB-T transmission modes, guard intervals, and bandwidth settings. Modulation parameters are extracted from the embedded Transmission and Multiplexing Configuration Control (TMCC) channel and used to dynamically configure the demodulator without the need for any intervention from the host microprocessor.
A test data capture facility at points along the signal chain and a flexible microprocessor interface aids easy integration with your system. The design is available now as an efficient implementation for Xilinx FPGAs. Other FPGA’s and ASICs can also be supported on request.
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