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ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
Dream Chip’s Real-time Pixel Processor (RPP) is a scalable and configurable High Dynamic Range (HDR) capable image signal processor (ISP), developed for high-performance imaging applications. The RPP_X2 processing pipeline consists of all necessary modules to produce HDR tone-mapped images of the highest possible quality.
In addition, the RPP provides measurement values in real time to implement 2A (auto exposure and auto white balance) functionality.
It accepts RGB Bayer input data in ITU-R BT.601 or ITU-R BT.656 sync mode and can be connected via MIPI serial interfaces. The RPP provides configurable input and output data widths. It supports 18MP input image frames 12-bit up to 26-bit amplitude resolutions, while it can output tone-mapped frames with 10 or 12 bits per pixel.
Until tone mapping, the data path supports full 26-bit accuracy.
Furthermore, the RPP provides a 26-bit DMA data interface as an alternative input path, and a 32-bit PVCI configuration interface. The input part of the ISP is fully programmable in terms of signal polarities, active video data positions, and luminance/chrominance or Bayer pattern order.
RPP_X2 can output various image data formats including Raw Bayer, RGB, XYZ, YCbCr and CIELuv.
The RPP ISP has two parallel outputs, one for human vision and one for machine vision.
The IP supports ASIL D (systematic) and ASIL B (hardware integrity) in accordance with ISO 26262:2018
In addition, the RPP provides measurement values in real time to implement 2A (auto exposure and auto white balance) functionality.
It accepts RGB Bayer input data in ITU-R BT.601 or ITU-R BT.656 sync mode and can be connected via MIPI serial interfaces. The RPP provides configurable input and output data widths. It supports 18MP input image frames 12-bit up to 26-bit amplitude resolutions, while it can output tone-mapped frames with 10 or 12 bits per pixel.
Until tone mapping, the data path supports full 26-bit accuracy.
Furthermore, the RPP provides a 26-bit DMA data interface as an alternative input path, and a 32-bit PVCI configuration interface. The input part of the ISP is fully programmable in terms of signal polarities, active video data positions, and luminance/chrominance or Bayer pattern order.
RPP_X2 can output various image data formats including Raw Bayer, RGB, XYZ, YCbCr and CIELuv.
The RPP ISP has two parallel outputs, one for human vision and one for machine vision.
The IP supports ASIL D (systematic) and ASIL B (hardware integrity) in accordance with ISO 26262:2018
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