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JESD204B /204C PHY&MAC
With sophisticated architecture and advanced technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high performance application. It is fully compatible with JESD204B/204C specification, and supports link rate up to 25Gbps per lane.
Take JESD204B TX IP as an example, which assembles the parallel data from the ADCs into frames and uses 8b/10b encoding, as well as optional scrambling, to form serial output data. For the MAC side, it has the transport layer, which handles packing the data into the JESD204B frames. Besides, the data link layer is responsible for the low level functions of passing data across the link. For the PMA side, it has four lanes and a common block.
Take JESD204B TX IP as an example, which assembles the parallel data from the ADCs into frames and uses 8b/10b encoding, as well as optional scrambling, to form serial output data. For the MAC side, it has the transport layer, which handles packing the data into the JESD204B frames. Besides, the data link layer is responsible for the low level functions of passing data across the link. For the PMA side, it has four lanes and a common block.
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