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JESD204D - Succesfully Taped out, Silicon Agnostic IP core
The JESD204D Controller IP is based on the recently released D revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204D IP core supports line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ and includes full backwards compatibility with 32.5 Gbps JESD204C.1 64b 66b link layer and 16 Gbps JESD204B 8b 10b link layer.
The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing.
The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing.
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Block Diagram of the JESD204D - Succesfully Taped out, Silicon Agnostic IP core
