LatticeMico32 Open, Free 32-Bit Soft Processor
By combining a 32-bit wide instruction set with 32 general purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Using a RISC architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set. To accelerate the development of microprocessor systems, several optional WISHBONE compatible peripheral components may be integrated with the LatticeMico32.
WISHBONE Compatible Peripheral Components
To accelerate the development of microprocessor systems, several optional WISHBONE compatible peripheral components may be integrated with the LatticeMico32.
* Memory controllers * DDR, DDR2 & DDR3 SDRAM
* Asynchronous SRAM
* On-chip Block Memory
* SDRAM controller
* On-chip dual port memory
* SPI Flash
* Parallel Flash
* I/O * 32-bit Timer
* DMA Controller
* GPIO
* I2C Master Controller
* SPI
* Tri-Speed Ethernet MAC
* UART
* PCI Target
Three Configurations to Optimize Area and Performance
* Basic * No Multiplier
* Multicycle Shifter
* No Cache
* Standard * Multiplier
* Pipelined Shifter
* 8K I-Cache, No D-Cache
* Full * Multiplier
* Pipelined Shifter
* 8K I-Cache, 8K D-Cache
Development Tools
LatticeMico System is to be used to implement a LatticeMico32 system with attached peripheral components. It is based on the Eclipse C/C++ Development Tools Environment, which is an industry open-source development and application framework for building software.
Supported Development Boards
Lattice has pre-defined a number of its development boards as platforms within the LatticeMico System Software. This allows you to rapidly start developing LatticeMico32 based systems on these boards. The following boards have been developed:
* LatticeMico32 Development Board for LatticeECP2
* LatticeMico32 Development Board for LatticeECP
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Block Diagram of the LatticeMico32 Open, Free 32-Bit Soft Processor
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