DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
LDO Capless Fast Response Series ( Vin = 3.0-3.6V; Vo = 1.05-1.15V; Io = 10mA ) - Toshiba 40nm
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LDO IP
- LDO Voltage Regulator, 30 mA, Adjustable 0.45 V to 0.9 V Output
- LDO Voltage Regulator, 250 mA, Adjustable 0.45 V to 0.9 V Output
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- LDO Linear Voltage Regulator
- Ultra-low quiescent LDO voltage regulator in TSMC 22ULL
- Capless 1.8V output LDO with 2.0-3.6V input range - 0.18 EF