Library of LVDS Ios cells in HLMC 28nm

This IP is a total solution for LVDS applications, including LVDS transmitter I/O, receiver I/O, common block and power/ground I/O. LVDS transmitter and receiver support 1.2Gbps maximum data-rate. LVDS transmitter I/O can obtain good impedance matching by setting internal terminal impedance enable. There are multi-bits controlling signals to get different differential output swings and common mode voltage.
LVDS receiver I/O can receive differential signals with full-scale common voltage and small differential voltage.

• see the entire Library of LVDS Ios cells in HLMC 28nm datasheet
• get in contact with Library of LVDS Ios cells in HLMC 28nm Supplier