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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
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Linear Low-Dropout Regulator (Output Voltage 0.9V)
1-VIA’s VSCOM4L400ALDO0V9 IP is a linear Low-Dropout (LDO) voltage regulator providing precise and programmable voltage regulation across a wide range of input and output voltages (0.81-1.02V, 8 configurations with 30mV trimmability in each configuration) implemented in TSMC12/16nm CMOS FinFET technology.
The regulator architecture provides high Power Supply Rejection (PSR) and low noise making it suitable for analog and RF applications.
The regulator architecture provides high Power Supply Rejection (PSR) and low noise making it suitable for analog and RF applications.
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Block Diagram of the Linear Low-Dropout Regulator (Output Voltage 0.9V)
Bandgap Voltage Reference IP
- Bandgap Voltage Reference (0.6V and 0.8V References)
- Ultra-Low-Power Bandgap Voltage Reference in 40nm CMOS
- Ultra-Low-Power Bandgap Voltage Reference in 28nm CMOS
- Ultra-Low-Power Bandgap Voltage Reference in 6nm CMOS
- Ultra-Low-Power Bandgap Voltage Reference in 12nm CMOS
- Accurate BandGap Voltage/Current Reference Generator