English
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
You are here:
Low (Leakage) Power Memory
The low power embedded SP SRAM is specifically architected and designed with mobile and IoT applications in mind that demands the lowest leakage power for maximum battery life.
View Low (Leakage) Power Memory full description to...
- see the entire Low (Leakage) Power Memory datasheet
- get in contact with Low (Leakage) Power Memory Supplier
Low (Leakage) Power Memory IP
- Single Port SRAM compiler - Memory optimized for ultra low leakage and high density - Dual Voltage - compiler range up to 640 k
- Ultra Low Leakage/Ultra Low Power Ternary-CAM/Binary-CAM, supports process ULL/ULP
- Ultra Low Leakage/Ultra Low Power Dual Port SRAM Compiler with Row/Column Redundancy Option, with write assist, supports process ULL/ULP
- Ultra Low Leakage/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, with read assist, write assist, supports process ULL/ULP
- Ultra Low Leakage/Ultra Low Power MultiBank Single Port SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, read assist, write assist, supports process ULL/ULP
- Ultra Low Leakage/Ultra Low Power Single Port Multi-banks SRAM Compiler with Row/Column Redundancy Option, with Low Leak support, short and long channel, inputs isolation, dual-rails, register scan, read assist, write assist, supports process ULL/ULP