Analog Bits’ Low Power Wide Range PLL addresses markets and applications that demand very low power and optimized for area efficiencies. In addition, consumer devices have restrictions on supply voltage due to battery restrictions or board restrictions. The PLLs are designed for standard digital logic processes and implement robust design techniques to work in noisy SoC environments. The PLLs can address a large portfolio of applications, ranging from non-integer clock multiplication to programmable clock synthesis for multi-clock generation.