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LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPCU) and an Analog PHY(APHY) part. The interface
between DRAM controller and the DDR PHY IP is compliant with DFI3.1(DDR PHY Interface) specification. The DDR PHY IP includes auto initialization and auto training engine for easy using, the auto data de-skew, hardware VT detection and hardware auto timing update functionalities make the DRAM memory system design become more stable and robust.
between DRAM controller and the DDR PHY IP is compliant with DFI3.1(DDR PHY Interface) specification. The DDR PHY IP includes auto initialization and auto training engine for easy using, the auto data de-skew, hardware VT detection and hardware auto timing update functionalities make the DRAM memory system design become more stable and robust.
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