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1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
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LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring high-performance LPDDR4, LPDDR3, DDR4, DDR3, and/or DDR3L SDRAM interfaces operating at up to 4,267 Mbps.
With multiple interfaces, the LPDDR4 multiPHY can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 or DDR3 SDRAMs.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR4 multiPHY is provided as hardened IP macrocells including a 4 slice Address/Command macrocell (ACX4), an 8-bit data macrocell (DBYTE) that includes DM/DBI and data strobes, and a master macrocell (MASTER) that includes the PLL used by the PHY. The macrocells include fully integrated I/Os and are easily assembled into a variety of configurations from a single 16-bit LPDDR4 PHY to a 72-bit DDR4 PHY. An RTL-based PHY utility block (PUB) with firmware-based training capabilities supports the GDSII-based PHY. In addition to training the interface after boot-
up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, and facilitates ATE testing and interface diagnostics. The LPDDR4 multiPHY includes a DFI
4.0 version 2 interface to the memory controller and can be combined with the Synopsys Enhanced Universal Memory or Protocol Controllers (uMCTL2 or uPCTL2) for a complete DDR interface solution.
With multiple interfaces, the LPDDR4 multiPHY can, for example, be used in a mobile application such as a smartphone that requires high-performance LPDDR4 mobile SDRAM support and also used in a larger form factor budget tablet application requiring DDR4 or DDR3 SDRAMs.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR4 multiPHY is provided as hardened IP macrocells including a 4 slice Address/Command macrocell (ACX4), an 8-bit data macrocell (DBYTE) that includes DM/DBI and data strobes, and a master macrocell (MASTER) that includes the PLL used by the PHY. The macrocells include fully integrated I/Os and are easily assembled into a variety of configurations from a single 16-bit LPDDR4 PHY to a 72-bit DDR4 PHY. An RTL-based PHY utility block (PUB) with firmware-based training capabilities supports the GDSII-based PHY. In addition to training the interface after boot-
up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, and facilitates ATE testing and interface diagnostics. The LPDDR4 multiPHY includes a DFI
4.0 version 2 interface to the memory controller and can be combined with the Synopsys Enhanced Universal Memory or Protocol Controllers (uMCTL2 or uPCTL2) for a complete DDR interface solution.
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