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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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LPDDR5/4/4X PHY in Samsung (14nm) for Automotive
The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package applications requiring high-performance LPDDR5, LPDDR4, and LPDDR4X SDRAM interfaces operating at up to 6400 Mbps. With multiple
interfaces and supporting a wide frequency range, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 or LPDDR4/4X SDRAMs, precisely targeting specific Power, Performance, and Area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as the following hardened IP components:
A single-bit macrocell (SE slice) for single-ended Command/Address (C/A) and Data (DQ) signals
A single-bit macrocell (DIFF slice) for differential signals (clock signals)
A single-bit macrocell (CMOS slice) for CMOS logic-level based C/A signals
A master macrocell (MASTER)
These macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility
Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the Synopsys LPDDR5/4/4X Universal Memory (uMCTL5) for a complete DDR interface solution.
interfaces and supporting a wide frequency range, the LPDDR5/4/4X PHY can be used in a variety of mobile applications supporting LPDDR5 or LPDDR4/4X SDRAMs, precisely targeting specific Power, Performance, and Area (PPA) requirements of these systems.
Optimized for high performance, low latency, low area, low power, and ease of integration, the LPDDR5/4/4X PHY is provided as the following hardened IP components:
A single-bit macrocell (SE slice) for single-ended Command/Address (C/A) and Data (DQ) signals
A single-bit macrocell (DIFF slice) for differential signals (clock signals)
A single-bit macrocell (CMOS slice) for CMOS logic-level based C/A signals
A master macrocell (MASTER)
These macrocells include fully integrated IOs and are easily assembled into a variety of configurations supporting a wide range of SoC DRAM interface requirements. Supporting the GDSII-based PHY is the RTL-based PHY Utility
Block (PUB) that features Synopsys’ unique firmware-based training capability. In addition to training the interface after boot-up, the PUB contains the configuration registers for the PHY, performs periodic delay line compensation against voltage and temperature drift, and facilitates ATE testing and interface diagnostics. The LPDDR5/4/4X PHY includes a DFI 5.0 interface to the memory controller and can be combined with the Synopsys LPDDR5/4/4X Universal Memory (uMCTL5) for a complete DDR interface solution.
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