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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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LVDS Transmitter
The transmitter is designed to support Single link transmission between Host and Flat Panel Display up to 1080p resolutions, Dual Link transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 70 bits of CMOS data into LVDS (Low Voltage Differential Signaling) data streams. Using a 150MHz clock, the data throughput is 10.5Gbps.
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Block Diagram of the LVDS Transmitter IP Core
LVDS Transmitter IP
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