English
You are here:
LVDS Transmitter IP, Tx IO, UMC 55nm SP process
0.18um TX PAD, UMC 0.18um Logic RVT-FSG process.
View LVDS Transmitter IP, Tx IO, UMC 55nm SP process full description to...
- see the entire LVDS Transmitter IP, Tx IO, UMC 55nm SP process datasheet
- get in contact with LVDS Transmitter IP, Tx IO, UMC 55nm SP process Supplier
LVDS IP
- Bi-Directional LVDS with LVCMOS
- TSMC 3nm (N3E) 1.5V LVDS
- TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Display LVDS/MIPI D-PHY/sub-LVDS combo Transmitter 1.0G/2.5G/1.0Gbps 10-Lane
- LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Display LVDS single link/dual link Transmitter 1.12Gbps 8-Lane