M31 Digital PLL IP in 3nm, 5nm, 6nm, 7nm, 12nm, 16nm, 22nm,28nm,40nm
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Digital PLL IP
- Ultra-Low Phase Noise Digital LC PLL
- Aeonic Generate Clock Generation Module [PLL], 8x smaller than fractional analog solutions
- 4-GHz Jitter-optimized low-power digital PLL
- 1.5-GHz Jitter-optimized low-power digital PLL
- 4-GHz Jitter-optimized low-power digital PLL
- High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS