Majority voting combination rule core with serial operation
So_ip_ecr_mv_s core can be used to implement the following Majority Voting combination rule variants: unanimous voting, simple majority voting, plurality voting and weighted majority voting.
So_ip_ecr_mv_s core should be used in conjunction with some ensemble evaluation module that is able to calculate the instance classifications for ensemble members sequentially, one at a time. Using these classifications, so_ip_ecr_mv_s core can calculate the combined classification of the current instance. Since the combination of the individual members classifications is done sequentially, the classification speed of this core is not so fast, but the core requires significantly less resources for the implementation.
So_ip_ecr_mv_s core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_ecr_mv_s design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_ecr_mv_s core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
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