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UCIE 2.0 Controller

• Compliant with UCIe 2.0 specification
• High bandwidth and low latency controller design

Doppler Channel IP Core

• Support for orbital heights (h) in the range from 200 to 2000 km
• Support for carrier frequencies ( fc) in the range from 137 to 2200 MHz

MIPI D-PHY Tx 4 Lanes on TSMC 7FF18 for Automotive

• Compliant with the MIPI D-PHY specification
• Fully verified hard macro
• Up to 2.5 Gb/s per lane

4K Video Scaler IP Core

• Technology independent soft IP Core for FPGA, SoC and ASIC devices
• Supplied as human readable VHDL source code (or Verilog on request)

Universal Chiplet Interconnect Express (UCIe) Controller

• Up to 32 GT/s Per Lane.
• Up to 512 Gbps Aggregate Bandwidth.
• Support PCIe 7.0/6.0 CXL Streaming mode.

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC

• Dual mode PHY Supports MIPI Alliance Specification D-PHY v3.5 & C-PHY v2.1
• Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
• Consists of 3 Data lanes in C-PHY mode

5.8GHz Fractional-N PLL synthesizer

• Power supply 1.3V…1.98V
• Fractional PLL
• Two-point frequency modulation (BFSK) support

PCIe 5.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)

• Fully integrated multi-protocol turnkey platform in TSMC 12nm FFC+ for integration into Smart Edge AIoT SoCs

UCIe-S PHY, Standard Package

• Compliant to UCIe 2.0 specifications
• Supports MCM, BGA and Chiplet2Chiplet interconnects on PCB
• Speed up to 32GT/s per lane (insertion loss and process dependent)

PCIe 6.2 Switch IP Controller

• Compliant with PCIE Gen6/5/4/3/2/1 spec
• Data rate supports Gen 1/2/3/4/5/6
• Pipe 64bits

ONFI 4.0 NAND Flash PHY upto 800Mbps

• ONFI 1/2/3/4/5 compliant;
• Toggle/Toggle2 mode;
• Maximum 2400Mbps; (PHY_CLK = 1200Mhz)

1.6T Ultra Ethernet IP Solution with PHY, Controller and Verification IP

• Ethernet MAC, PCS and PHY to complete a full Ultra Ethernet interface stack
• Supports evolving IEEE 802.3 and OIF-224G electrical standards

On-chip Security Enclave - Digital IP delivered as RTL

• Fully digital IP delivered as RTL and hence can be used on all digital logic silicon nodes with the required foundry memories inc. OTP
• Support for external secure NVM

28G Ethernet PHY IP for TSMC N7

• Supports 1.25 to 32 Gbps data-rate
• Supports PCI Express 5.0, 1G to 400G Ethernet, CCIX, CXL, and SATA protocols

Embedded Hardware Security Module (EVITA-Full Compliant)

• Pre-integrated CPU
• Full suite of hardware-accelerate cryptographic engine (Meet EVITA-Full requirements)

UALink IP Solution with PHY, Controller and Verification IP

• Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
• Complete UALink IP solution with Controller, PHY and VIP, fully integrated for AI accelerators (XPUs), GPUs, and switches

5-60V Input Buck Regulator (Type-C EPR compatible)

• Wide operating voltage range 4.5V – 60V.
• Output voltage optionally 5V, or 3.3V.
• Soft start.

UCIe PHY & D2D Adapter

• 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
• UCIe v1.1 specification

USB4 PHY in TSMC (N7, N6, N5, N3E)

Low Power Dual PHY for UCIe low cost robust Chiplets

• Support standard chiplet use for UCIe standard to 16G
• Supports Chip Scale Packaging with 250V ESD option
• Build in Security and Probe function for KGD

2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

• Efficiency
• Composability
• Programmability

UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect

• Emerging Standard Knowledge
• Flexibly Configurable
• Best in Class PPA

USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)