English
You are here:
MIPI A-PHY Sink/Source IP (1-Lane)
The Teletrx_7999 is compliant with MIPI A-PHY interface specification version 1.1. It features application on ADAS/ADS surround asymmetric sensor connectivity, meeting ultra-high speed performance and long reach requirement.
The IP contains 1 Lane Sink/Source and supports up to 8Gbps data rate. It includes clean common clock source, high performance equalizer, high jitter-tolerance clock and data recovery in RX. TX has high quality driver and supports parallel 16bit data bus width on interface. Also support uplink driver@100MHz. For test and debug purpose, analog monitor port is built in.
This MIPI A-PHY IP has low power and small area advantages by advanced process TSMC 22nm process node.
The IP contains 1 Lane Sink/Source and supports up to 8Gbps data rate. It includes clean common clock source, high performance equalizer, high jitter-tolerance clock and data recovery in RX. TX has high quality driver and supports parallel 16bit data bus width on interface. Also support uplink driver@100MHz. For test and debug purpose, analog monitor port is built in.
This MIPI A-PHY IP has low power and small area advantages by advanced process TSMC 22nm process node.
View MIPI A-PHY Sink/Source IP (1-Lane) full description to...
- see the entire MIPI A-PHY Sink/Source IP (1-Lane) datasheet
- get in contact with MIPI A-PHY Sink/Source IP (1-Lane) Supplier