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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 v1.2 and display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-C v1.0 applications in the C-PHY mode. The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
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Block Diagram of the MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
Video Demo of the MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
Mixel, in collaboration with Rambus and Hardent, demonstrates an integrated display IP subsystem solution that combines the Mixel MIPI D-PHY℠ DSI TX IP, Rambus MIPI DSI-2℠ host controller, and Hardent VESA Display Stream Compression (DSC) IP. This complete solution targets display applications requiring high bandwidth and excellent power efficiency for mobile, AR/VR and automotive.
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)