MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY

The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destination for each data packet (Bayer input of ISP, RGB/YUV input of ISP, Memory). The IP reorders up to 4 x 1Gbps data lanes, separates sensor clock of CSI-2 Core from DPHY byte clock and merges active ones into 32 bits words. The
IP Core is able to store in memory all CSI2 datatype and to process rawbayer, compressed rawbayer, yuv pixel reconstruction for on-the-fly ISP processing. It also performs ECC/CRC check & correction and provides data to SMIA.CSI-2 Receiver IP supports Virtual Channel and Datatype selection. It supports continuous and gated clock configurations

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