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MIPI CSI-2 RX Controller for v2.1
CSI-2 receiver controller for application processor
The Cadence® Receiver (RX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is responsible for handling and decoding CSI-2 protocol-based camera or other sensor data streams received via a MIPI D-PHYSM link and managing the forwarding or unpacking of payload data to the pixel stream interfaces. The RX Controller IP for CSI-2 allows the selection of multiple independent streams to support the control of the destination for each data packet (for example, Bayer input of ISP, RGB/YUV input of ISP, or DMA to memory). Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the RX Controller IP for CSI-2 is engineered to quickly and easily integrate into any system-on-chip (SoC) design, and to connect seamlessly to a Cadence or thirdparty D-PHY via a standard PHY-Protocol Interface (PPI). The RX Controller IP for CSI-2 is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.
The Cadence® Receiver (RX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is responsible for handling and decoding CSI-2 protocol-based camera or other sensor data streams received via a MIPI D-PHYSM link and managing the forwarding or unpacking of payload data to the pixel stream interfaces. The RX Controller IP for CSI-2 allows the selection of multiple independent streams to support the control of the destination for each data packet (for example, Bayer input of ISP, RGB/YUV input of ISP, or DMA to memory). Developed by experienced teams with industry-leading domain expertise and extensively validated with multiple hardware platforms, the RX Controller IP for CSI-2 is engineered to quickly and easily integrate into any system-on-chip (SoC) design, and to connect seamlessly to a Cadence or thirdparty D-PHY via a standard PHY-Protocol Interface (PPI). The RX Controller IP for CSI-2 is part of the comprehensive Cadence Design IP portfolio comprised of interface, memory, analog, and system and peripheral IP.
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