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MIPI CSI-2 Rx Controller
Features
- PPI Interface according to MIPI Alliance Standard for Camera Serial Interface 2
- Supports up to 4 data lanes
- Number of lanes is programmable and hardware configurable
- Provides lane merging, error detection and correction, virtual channel detection, programmable data extraction and embedded data separation
- Supported Data Types are
- Generic 8bit Data
- non-legacy YUV 4:2:0 8bit / 10bit with cosited chroma sampling
- non-legacy YUV 4:2:0 8bit / 10bit with non-cosited chroma sampling
- legacy YUV 4:2:0 8bit
- YUV 4:2:2 8bit / 10bit
- RGB 444 / 555 / 565 / 666 / 888 image data
- RAW 6-bit / 7-bit / 8-bit / 10-bit / 12-bit image data
- User defined 8-bit data
- Compressed data types as defined in CSI-2 version 1.01 draft (2-Oct-200)
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MIPI CSI-2 IP
- MIPI CSI-2 Controller Core V2
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY Universal IP in TSMC 22ULP
- MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6