Scalable, On-Die Voltage Regulation for High Current Applications
MIPI CSI2 Transmit Controller
The CSI-2 Transmitter receives pixels by way of the ISP Interface or packed data by way of the PDI Interface. The CSI-2 Transmit Controller converts pixels into a byte stream, calculates and appends an ECC value to a short packet or to the header of a long packet. Packets are buffered in a FIFO and synchronized to the High-Speed Byte clock domain and sent to one or more of D-PHY lanes depending upon the lane distribution scheme set by the camera sensor.
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Block Diagram of the MIPI CSI2 Transmit Controller IP Core
