MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP

The MXL-DPHY-CSI-2-RX-T-065LP is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

• see the entire MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP datasheet
• get in contact with MIPI D-PHY CSI-2 RX (Receiver) in TSMC 65LP Supplier