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MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM
The MXL-DPHY-CSI-2-RX+ is a high frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI slave optimized for camera interface applications (CSI2).
The RX+ is a Mixel proprietary D-PHY configuration that enables Mixel's customers to achieve full-speed testability while minimizing power and area.
The IP is configured as a MIPI slave optimized for camera interface applications (CSI2).
The RX+ is a Mixel proprietary D-PHY configuration that enables Mixel's customers to achieve full-speed testability while minimizing power and area.
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Block Diagram of the MIPI D-PHY CSI-2 RX+ (Receiver) IP in TSMC 28HPM
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)