English
You are here:
MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP
The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY.
The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
The IP is configured as a MIPI master optimized for camera interface applications (CSI-2).
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
View MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP full description to...
- see the entire MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP datasheet
- get in contact with MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP Supplier
Block Diagram of the MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP
Video Demo of the MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 65LP
We demonstrate our customer demo, the Microsoft Azure Kinect DK, featuring the Mixel MIPI D-PHY CSI-2 TX IP.
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)