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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
The MXL-DPHY-CSI-2-TX+-T-40ULP is a high-frequency, low-power, low-cost, source synchronous physical Layer supporting the MIPI Alliance Specification for D-PHY v2.1.
The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in system testing while minimizing area and leakage power.
The PHY can be configured as a MIPI Master supporting camera interface CSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications. The CSI-2 TX+ is a Mixel proprietary configuration that is optimized to support full-speed production and in system testing while minimizing area and leakage power.
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Block Diagram of the MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
Video Demo of the MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
Mixel’s MIPI D-PHY CSI-2 TX+ IP integrated into ams OSRAM's Mira050 CMOS Image Sensor.
The ams OSRAM Mira product family of CMOS imaging sensors serves a broad range of applications and markets including eye tracking, gesture tracking, bar code scanning, robotic mobility, 3D Structured Light, 3D Active Stereo systems and 2D NIR imaging. To deliver these applications, a focus on small footprint and high system power efficiency is critical.
Mixel provided ams OSRAM with the Mixel MIPI D-PHY CSI-2 TX+ IP, which enabled ams OSRAM to achieve first-time silicon success. The MIPI solution includes two IP products delivered fully integrated and validated: Mixel’s MIPI D-PHY(SM) transmitter and a 32-bit MIPI CSI-2® TX Controller Core.
More information can be found here: https://mixel.com/mixel-mipi-ip-ams-osram-mira-image-sensor/