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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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MIPI D-PHY DSI 1.2G RX IP
Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communication protocols defined by MIPI® Alliance, which is intended for mobile system chip to chip communications. The MIPI DSI specification is specifically targeted for the display communications in image application processors.
Innosilicon MIPI DSI receiver operates as a receiver of a DSI link, which consists of a MIPI D-PHY and a DSI controller.
The MIPI D-PHY is used for the data transmission from a DSI compliant display module. In D-PHY, data streams are organized as packets. Error information is generated for the application layer to do further operation.
The DSI controller works as a protocol layer between the application layer and physical layer, which aims to reconstruct the data streams from the D-PHY. Innosilicon DSI controller implements all three layers defined by DSI specification, including Pixel/Byte Packing, Low Level Protocol, and Lane Management.
Innosilicon MIPI DSI receiver operates as a receiver of a DSI link, which consists of a MIPI D-PHY and a DSI controller.
The MIPI D-PHY is used for the data transmission from a DSI compliant display module. In D-PHY, data streams are organized as packets. Error information is generated for the application layer to do further operation.
The DSI controller works as a protocol layer between the application layer and physical layer, which aims to reconstruct the data streams from the D-PHY. Innosilicon DSI controller implements all three layers defined by DSI specification, including Pixel/Byte Packing, Low Level Protocol, and Lane Management.
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