MIPI D-PHY - TSMC 40nm LP

The T40LP_MIPIDPHYV01 IP is a MIPI D-PHY and LVDS based on TSMC 40nm LP process. It is suitable for the interface between the timing controller and column drivers.

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Block Diagram of the MIPI D-PHY - TSMC 40nm LP

MIPI IP

MIPI CSI-2 Controller Core V2
MIPI DSI-2 Controller Core
MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
I3C Host Controller
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
MIPI DSI Receiver Controller v1.3

See more MIPI IP >>

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