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MIPI D-PHY
Features
- Compliant with the MIPI D-PHY spec v2.5
- Fully integrated hard macro with lane control and interface logic
- Up to 1.5 Gbps per lane with upgradable option to 2.5 Gbps per lane
- Supports PHY Protocol Interface (PPI)
- Low-power escape modes and ultra low-power state modes
View MIPI D-PHY full description to...
- see the entire MIPI D-PHY datasheet
- get in contact with MIPI D-PHY Supplier
MIPI D-PHY IP
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI DSI Receiver Controller v1.3
- MIPI DSI Transmit Controller v1.3
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)