MIPI D-PHY Rx IP, Silicon Proven in GF 55LP

Version 1.2 of the D-PHY specification is fully complied with by the MIPI D-PHY Analog RX IP Core. Both the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols can be used. This RX PHY is configured with one clock channel and four data lanes. The D-PHY comprises of a digital back end for managing I/O operations and an analogue front end for sending and receiving electrical level signals. The intrinsic resistor is automatically terminated.

• see the entire MIPI D-PHY Rx IP, Silicon Proven in GF 55LP datasheet
• get in contact with MIPI D-PHY Rx IP, Silicon Proven in GF 55LP Supplier