The D-PHY specification, version 1.2, is perfectly complied with by the MIPI D-PHY Analog RX IP Core. Supported protocols include the Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2). This RX PHY consists of one clock lane and four data lanes. The D-PHY is made up of an analogue front end for creating and receiving electrical level signals and a digital back end for managing I/O operations. internally terminated resistor that is automatically calibrated.