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MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2. It supports both the Display Serial Interface (DSI) and the MIPI Camera Serial Interface (CSI-2) protocols. The RX PHY comprises four data lanes and one clock lane.
The D-PHY includes a digital backend for managing I/O operations and an analog frontend for generating and receiving electrical level signals, incorporating an intrinsic resistor that is automatically terminated.
The D-PHY includes a digital backend for managing I/O operations and an analog frontend for generating and receiving electrical level signals, incorporating an intrinsic resistor that is automatically terminated.
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Block Diagram of the MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
MIPI D-PHY Rx IP Core IP
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