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MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
The D-PHY specification, version 1.2, is fully complied with by the MIPI D-PHY Analog RX IP Core. It is possible to use the Display Serial Interface (DSI) and MIPI Camera Serial Interface (CSI-2) protocols. This RX PHY consists of four data lanes and one clock lane.
The D-PHY comprises of an analogue front end for creating and receiving electrical level signals and a digital back end for managing I/O operations. automatic termination of the intrinsic resistor.
The D-PHY comprises of an analogue front end for creating and receiving electrical level signals and a digital back end for managing I/O operations. automatic termination of the intrinsic resistor.
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Block Diagram of the MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
