MIPI D-PHY Universal IP in Samsung 28FDSOI

Block Diagram of the MIPI D-PHY Universal IP in Samsung 28FDSOI

Video Demo of the MIPI D-PHY Universal IP in Samsung 28FDSOI

In this Mixel customer demo video, we see Mixel’s MIPI D-PHY IP integrated into the Lattice CrossLink-NX FPGA, the world’s first low-power FPGA to support D-PHY v1.2 with 2.5Gbps per lane and the previous generation FPGA, Lattice Crosslink which was the first bridge supporting 12 Gbps of Aggregate Bandwidth.

Built using the new 28 nm FD-SOI Lattice Nexus™ FPGA platform, the CrossLink-NX FPGAs outperform FPGAs of similar class in terms of power, form factor, reliability, and performance. The CrossLink-NX FPGAs were developed for use in applications including sensor and display bridging, sensor aggregation, sensor duplication, and AI inferencing at the Edge.

The previous generation Lattice CrossLink bridge combines the flexibility and fast time to market of an FPGA with the power and functional optimization of an ASSP to create a new product class called programmable ASSP (pASSP™). This solution, which is now going into production, integrates Mixel’s high performance, low power Universal MIPI D-PHY, implemented in UMC’s 40nm process to achieve first silicon success.