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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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MIPI D-PHY Universal IP in UMC 40LP
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI Alliance Standard for D-PHY.
The IP can be configured as a MIPI Master or MIPI Slave optimized for camera interface (CSI-2) and display (DSI) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low powerfunctions are mostly used for control.
The IP can be configured as a MIPI Master or MIPI Slave optimized for camera interface (CSI-2) and display (DSI) applications.
The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low powerfunctions are mostly used for control.
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Block Diagram of the MIPI D-PHY Universal IP in UMC 40LP
Video Demo of the MIPI D-PHY Universal IP in UMC 40LP
We demonstrate our customer demo, the Lattice Crosslink FPGA Video Bridge, featuring Mixel's MIPI D-PHY Universal IP.
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